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asahi kasei [ak4523] m0021-e-03 1999/12 - 1 - general description the ak4523 has a dynamic range of 100db and is well-suited middle-range md, surround system, musical instruments and car audio. signal inputs and outputs are single-ended. the dac outputs are analog filtered to remove out of band noise. external components are minimized. features o ds stereo adc - 64x oversampling - sample rate ranging from 16khz to 48khz - s/(n+d): 92db - dynamic range, s/n: 100db - digital hpf for offset cancellation o ds stereo dac - 128x oversampling - sampling rate ranging from 16khz to 48khz - 2nd order scf + 2nd order ctf - digital de-emphasis for 32khz, 44.1khz, 48khz sampling - s/(n+d): 90db - dynamic range, s/n: 100db - soft mute o high jitter tolerance o master clock: 256fs, 384fs, 512fs o analog power supply: 4.5 to 5.5v, digital power supply: 3.0 to 5.5v va agnd vd dgnd cmode ainl+ ainl- ainr+ ainr- vrefh vcom aoutl aoutr mcki lrck sclk sdto sdti dif0 dif1 smute dem1 dem0 pd modulator ds modulator ds filter decimation filter decimation hpf hpf common volta g e lpf lpf modulator ds modulator ds interpolator 8x interpolator 8x serial i/o interface clock divider 20bit stereo ds adc & dac ak4523
asahi kasei [ak4523] m0021-e-03 1999/12 - 2 - n ordering guide ak4523vf -40 ~ +85 c 28pin vsop (0.65mm pitch) AKD4523 evaluation board for ak4523 n pin layout agnd vrefh ainr+ ainr- ainl+ ainl- va nc nc dif0 dif1 lrck sclk sdti sdto smute dem0 dem1 nc vd dgnd pd cmode aoutl aoutr vcom mcki nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ak4523 top view n difference between ak4523 and ak4522 ak4523 ak4522 digital power supply 3.0 ~ 5.5v 2.7 ~ 5.5v ambient operating -40 ~ 85 c-10 ~ 70 c package 28pin vsop 24pin vsop
asahi kasei [ak4523] m0021-e-03 1999/12 - 3 - pin/function no. pin name i/o function 1 vrefh i positive voltage reference input pin, va used as a positive voltage reference by adc & dac. vrefh should be connected externally to filtered va. 2 ainr+ i rch analog positive input pin 3 ainr- i rch analog negative input pin 4 ainl+ i lch analog positive input pin 5 ainl- i lch analog negative input pin 6 va - analog power supply pin 7 agnd - analog ground pin 8 nc - no connect no internal bonding. 9 nc - no connect no internal bonding. 10 dif0 i audio data interface format 0 pin 11 dif1 i audio data interface format 1 pin 12 lrck i input channel clock pin 13 sclk i audio serial data clock pin 14 sdti i audio serial data input pin 15 sdto o audio serial data output pin 16 smute i soft mute pin when this pin goes h, soft mute cycle is initiated. when returning l, the output mute releases. 17 dem0 i de-emphasis frequency select 0 pin 18 dem1 i de-emphasis frequency select 1 pin 19 mcki i master clock input pin 20 nc - no connect no internal bonding. 21 nc - no connect no internal bonding. 22 vd - digital power supply pin 23 dgnd - digital ground pin 24 pd i power-down mode pin 25 cmode i master clock select pin (internal biased pin) h: 384fs, l: 256fs, nc: 512fs 26 aoutl o lch analog output pin 27 aoutr o rch analog output pin 28 vcom o common voltage output pin, va/2 note: all input pins except for cmode pin should not be left floating.
asahi kasei [ak4523] m0021-e-03 1999/12 - 4 - absolute maximum ratings (agnd, dgnd=0v; note 1) parameter symbol min max units power supplies analog digital |agnd-dgnd| (note 2) va vd d gnd -0.3 -0.3 - 6.0 6.0 0.3 v v v input current, any pin except supplies iin - 10 ma analog input voltage vina -0.3 va+0.3 v digital input voltage vind -0.3 vd+0.3 v ambient temperature (power applied) ta -40 85 c storage temperature tstg -65 150 c note:1. all voltages with respect to ground. 2. agnd and dgnd must be same voltage. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (agnd, dgnd=0v; note 1) parameter symbol min typ max units power supplies (note 3) analog digital va vd 4.5 3.0 5.0 5.0 5.5 va v v voltage reference vrefh 90%va va v note:1. all voltages with respect to ground. 3. the power up sequence between va and vd is not critical. *akm assumes no responsibility for the usage beyond the conditions in this datasheet.
asahi kasei [ak4523] m0021-e-03 1999/12 - 5 - analog characteristics (ta=25 c; va, vd=5v; agnd=dgnd=0v; vrefh=va; fs=44.1khz; sclk=64fs; signal frequency =1khz; 20bit data; measurement frequency=10hz ~ 20khz; unless otherwise specified) parameter min typ max units adc analog input characteristics: differential inputs; analog source impedance=470 w resolution 20 bits s/(n+d) (-0.5db input) (note 4) 84 92 db dr (-60db input, a-weighted) (note 5) 94 100 db s/n (a-weighted) (note 5, 6) 94 100 db interchannel isolation 90 110 db interchannel gain mismatch 0.1 0.3 db gain drift 20 ppm/ c input voltage (ain=0.6 x vrefh) (note 7) 2.85 3.0 3.15 vpp input resistance 15 25 k w power supply rejection (note 8) 50 db dac analog output characteristics: resolution 20 bits s/(n+d) 80 90 db dr (-60db output, a-weighted) (note 5) 94 100 db s/n (a-weighted) (note 6, 9) 94 100 db interchannel isolation 90 110 db interchannel gain mismatch 0.2 0.5 db gain drift 20 ppm/ c output voltage (aout=0.58 x vrefh) 2.65 2.9 3.15 vpp load resistance 5 k w load capacitance 25 pf power supply rejection (note 8) 50 db power supplies power supply current (va=vd=5v) analog, va pd = h 42 55 ma digital, vd pd = h 10 20 ma power down pd = l (note 10) 0.4 2 ma note: 4. in case of single ended input, s/(n+d)=80db(typ, @va=5v). 5. in case of 16bit, dr and s/n of adc are 98db. dr of dac is 98db. 6. s/n measured by ccir-arm is 96db at each converter and 94db at adc to dac loopback. 7. full scale input for each ain+/- pin is 1.5vpp in differential mode. 8. psr is applied to va, vd with 1khz, 50mvpp. vrefh pin is held a constant voltage. 9. as the input data is 0, s/n is 100db regardless of resolution. 10. all digital input pins are held vd or dgnd.
asahi kasei [ak4523] m0021-e-03 1999/12 - 6 - filter characteristics (ta=25 c; va=4.5 ~ 5.5v, vd=3.0 ~ 5.5v; dem0=1, dem1=0) parameter symbol min typ max units adc digital filter (decimation lpf): passband (note 11) -0.005db -0.02db -0.06db -6.0db pb 0 0 0 0 19.76 20.02 20.20 22.05 khz khz khz khz stopband sb 24.34 khz passband ripple pr 0.005 db stopband attenuation sa 80 db group delay (note 12) gd 29.3 1/fs group delay distortion d gd 0s adc digital filter (hpf): frequency response (note 5) -3db -0.5db -0.1db fr 0.9 2.7 6.0 hz hz hz dac digital filter: passband (note 11) -0.06db -6.0db pb 0 0 20.0 22.05 khz khz stopband sb 24.1 khz passband ripple pr 0.06 db stopband attenuation sa 43 db group delay (note 12) gd 14.7 1/fs dac digital filter + analog filter: frequency response: 0 ~ 20.0khz fr - 0.2 -db note:11. the passband and stopband frequencies scale with fs. for example, 20.02khz at -0.02db is 0.454 x fs. the reference frequency of these responses is 1khz. 12. the calculating delay time which occurred by digital filtering. this time is from the input of analog signal to setting the 20bit data of both channels to the output register for adc. for dac, this time is from setting the 20bit data of both channels on input register to the output of analog signal.
asahi kasei [ak4523] m0021-e-03 1999/12 - 7 - digital characteristics (ta=25 c; va=4.5 ~ 5.5v, vd=3.0 ~ 5.5v) parameter symbol min typ max units high-level input voltage (except cmode pin) low-level input voltage (except cmode pin) vih vil 70%vd - - - - 30%vd v v high-level input voltage (cmode pin) low-level input voltage (cmode pin) vih vil 95%vd - - - - 10%vd v v hight-level output voltage (iout=-80a) low-level output voltage (iout=80a) voh vol vd-0.4 - - - - 0.4 v v input leakage current (note 13) iin - - 10 a note: 13. cmode pin has internal pull-up and pull-down devices, nominally 50kohm.
asahi kasei [ak4523] m0021-e-03 1999/12 - 8 - switching characteristics (ta=25 c; va=4.5 ~ 5.5v; vd=3.0 ~ 5.5v; c l =20pf) parameter symbol min typ max units master clock timing 256fs: pulse width low pulse width high 384fs: pulse width low pulse width high 512fs: pulse width low pulse width high fclk tclkl tclkh fclk tclkl tclkh fclk tclkl tclkh 4.096 27 27 6.144 20 20 8.192 15 15 12.288 18.432 24.576 mhz ns ns mhz ns ns mhz ns ns lrck timing frequency duty cycle fs dfs 16 45 48 55 khz % serial interface timing sclk period sclk pulse width low pulse width high lrck edge to sclk - (note 14) sclk - to lrck edge (note 14) lrck to sdto (msb) sclk to sdto sdti hold time sdti setup time tsck tsckl tsckh tlrs tslr tlrm tssd tsdh tsds 320 65 65 45 45 40 25 40 70 ns ns ns ns ns ns ns ns ns reset timing pd pulse width (note 15) pd - to sdto valid (note 16) tpd tpdv 150 516 ns 1/fs note 14. sclk rising edge must not occur at the same time as lrck edge. 15. the ak4523 can be reset by bringing pd l. when the state of cmode change during operation, the ak4523 should be reset by pd . 16. these cycles are the number of lrck rising from pd rising.
asahi kasei [ak4523] m0021-e-03 1999/12 - 9 - n timing diagram tlrs lrck 50%vd sclk tlrm sdto 50%vd tssd 50%vd tslr tsds sdti 50%vd tsdh tslkl tslkh serial interface timing tpd 30%vd pd 70%vd sdto tpdv reset & initialize timing
asahi kasei [ak4523] m0021-e-03 1999/12 - 10 - operation overview n system clock the master clock (mclk) can be external clock input to the mcki pin. cmode is used to select either mclk=256fs, 384fs or 512fs. the relationship between the mclk and the desired sample rate is defined in table 1. the lrck clock input must be synchronized with mclk, however the phase is not critical. internal timing is synchronized to lrck upon power-up. all external clocks must be present unless pd = l, otherwise excessive current may result from abnormal operation of internal dynamic logic. mclk sclk fs 256fs cmode = l 384fs cmode = h 512fs cmode = nc 64fs 32.0khz 8.1920mhz 12.2880mhz 16.384mhz 2.048mhz 44.1khz 11.2896mhz 16.9344mhz 22.579mhz 2.822mhz 48.0khz 12.2880mhz 18.4320mhz 24.576mhz 3.072mhz table 1. system clock example when the state of cmode change under operation, the ak4523 should be reset by pd . at that case, the analog outputs should be muted externally because some click noise may occur.
asahi kasei [ak4523] m0021-e-03 1999/12 - 11 - n audio serial interface format data is shifted in/out the sdti/sdto pins using sclk and lrck inputs. four serial data modes selected by the dif0 and dif1 pins are supported as shown in table 2. in all modes the serial data has msb first, 2s compliment format. the data is clocked out on the falling edge of sclk and latched on the rising edge. for mode 3, if sclk is 32fs, then the least significant bits will be truncated. mode dif1 dif0 sdto (adc) sdti (dac) l/r sclk (slave) 0 0 0 20bit, msb justified 16bit, lsb justified h/l 3 32fs 1 0 1 20bit, msb justified 20bit, lsb justified h/l 3 40fs 2 1 0 20bit, msb justified 20bit, msb justified h/l 3 40fs 3 1 1 iis (i2s) iis (i2s) l/h 32fs or 3 40fs table 2. serial data modes lrck ( i ) sclk ( i:64fs ) sdto ( o ) 012 19 17 18 20 31 0 1 2 19 17 18 20 31 0 19 1 18 0 19 18 3 2 0 19 sdti ( i ) 1 14 0 12 11 1 14 0 12 11 sdto-19:msb, 0:lsb; sdti-15:msb, 0:lsb lch data rch data dont care dont care 32 sclk ( i:32fs ) sdto ( o ) 0 1 2 9 10 12 13 15 0 1 2 9 10 12 13 15 0 19 1 18 8 19 18 8 11 10 19 sdti ( i ) 1 60 43 1 15 0 54 11 10 2 54 76 17 15 14 13 31114 9 5 7 17 1 13 15 30 17 33 17 14 13 7 6 3 2 15 14 11 4 5 6 7 9 1 15 13 2 2 figure 1. mode 0 timing lrck(i) sclk(i:64fs) sdto(o) 0 1 2 12 13 14 20 21 31 0 1 2 12 13 14 20 21 31 0 19 1 18 0 19 18 8 7 6 0 19 sdti(i) 1 18 0 19 12 11 1 18 0 19 12 11 19:msb, 0:lsb lch data rch data dont care dont care 876 figure 2. mode 1 timing
asahi kasei [ak4523] m0021-e-03 1999/12 - 12 - lrck(i) sclk(i:64fs) sdto ( o ) 0 1 2 17 18 19 20 0 1 2 17 18 20 19 0 19 1 18 2 19 18 3 2 3 2 19 sdti(i) 18 19 1 0 1 22 0 23 1 0 19:msb, 0:lsb lch data rch data dont care dont care 3 32 21 21 19 10 figure 3. mode 2 timing lrck ( i ) sclk ( i:64fs ) sdto ( o ) 012 19 17 18 20 31 0 1 2 19 17 18 20 31 0 1 19 1 19 4 3 1 sdti ( i ) 310 310 19:msb, 0:lsb lch data rch data dont care dont care 43 sclk ( i:32fs ) sdto ( o ) 0 1 2 9 10 12 13 15 0 1 2 9 10 12 13 15 0 4 1 19 9 419 9 12 11 4 sdti ( i ) 12 11 65 87 18 31114 10 18 2 2 4 21 18 33 18 14 11 5 6 7 8 10 2 42 0 0 19 18 19 18 21 figure 4. mode 3 timing n digital high pass filter the adc of ak4523 has a digital high pass filter for dc offset cancel. the cut-off frequency of the hpf is 0.9hz at fs=44.1khz and also scales with sampling rate (fs).
asahi kasei [ak4523] m0021-e-03 1999/12 - 13 - n de-emphasis filter the dac of ak4523 includes the digital de-emphasis filter (tc=50/15s) by iir filter. this filter corresponds to three frequencies (32khz, 44.1khz and 48khz). the de-emphasis filter selected by dem0 and dem1 is enabled for input audio data. the de-emphasis is also disabled at dem0=1 and dem1=0. dem1 dem0 mode 0 0 44.1khz 01off 1 0 48khz 1 1 32khz table 3. de-emphasis filter control n soft mute operation soft mute operation is performed at digital domain. when smute goes to h, the output signal is attenuated by - during 1024 lrck cycles. when smute is returned to l, the mute is cancelled and the output attenuation gradually changes to 0db during 1024 lrck cycles. if the soft mute is cancelled within 1024 lrck cycles after starting the operation, the attenuation is discontinued and returned to 0db. the soft mute is effective for changing the signal source without stopping the signal transmission. smute attenuation 1024/fs 0db - 1024/fs gd gd (1) (2) (3) -100db noise level notes: (1) the output signal is attenuated by - during 1024 lrck cycles (1024/fs). (2) analog output corresponding to digital input has the group delay (gd). (3) if the soft mute is cancelled within 1024 lrck cycles, the attenuation is discontinued and returned to 0db. figure 5. soft mute operation
asahi kasei [ak4523] m0021-e-03 1999/12 - 14 - n power-down & reset the adc and dac of ak4523 are placed in the power-down mode by bringing a power down pin, pd l and each digital filter is also reset at the same time.this reset should always be done after power-up. in case of the adc, an analog initialization cycle starts after exiting the power-down mode. therefore, the output data, sdto becomes available after 516 cycles of lrck clock. this initialization cycle does not affect the dac operation. figure 6 shows the power-up sequence. adc internal state pd 516/fs normal operation power-down init cycle normal operation (1) the clocks may be stopped. gd gd clock in mclk,lrck,sclk adc in (analog) 0data adc out (digital) normal operation power-down normal operation dac internal state 0data dac in (digital) dac out (analog) gd external mute mute on gd (2) (2) (3) (4) (5) (5) (6) (1) the analog part of adc is initialized after exiting the power-down state. (2) digital output corresponding to analog input and analog output corresponding to digital input have the group delay (gd). (3) adc output is 0 data at the power-down state. (4) small click noise occurs at the end of initialization of the analog part. please mute the digital output externally if the click noise influences system application. (5) click noise occurs at the edge of pd . (6) please mute the analog output externally if the click noise (5) influences system application. figure 6. power-up sequence
asahi kasei [ak4523] m0021-e-03 1999/12 - 15 - system design figure 7 shows the system connection diagrams. this is an example which analog signal is input by single ended circuit. in case of differential input, please refer to figure 10. an evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. 4 3 2 1 vrefh ainr+ ainr- ainl+ ainl- 5 va 6 agnd 7 nc 8 nc 9 dif0 10 dif1 11 lrck 12 vcom 28 aoutr 27 aoutl 26 cmode 25 pd 24 dgnd 23 vd 22 nc 21 nc 20 mcki 19 dem1 18 dem0 17 ak4523 10u 0.1u + mode setting audio controller format settin g 4.5 ~ 5.5v analog supply + 10u 0.1u 470 470 4.7u 0.1u 2.2n 4.7u 0.1u 2.2n + + 0.1u + 3.0 ~ 5.5v digital supply 5 10u 0.1u sclk sdti 16 15 smute sdto 14 13 figure 7. typical connection diagram
asahi kasei [ak4523] m0021-e-03 1999/12 - 16 - analog ground vrefh ainr+ ainr- ainl+ ainl- va agnd nc nc dif0 dif1 lrck vcom aoutr aoutl cmode pd dgnd vd nc nc mcki dem1 dem0 ak4523 sclk sdti smute sdto 1 2 3 4 5 6 7 8 9 10 11 12 14 13 16 15 28 27 26 25 24 23 22 21 20 19 18 17 digital ground system controller figure 8. ground layout 5v analog 5v digital va vd vd system controller ak4523 5v analog 3v digital va vd vd system controller ak4523 case 1. 5v system case 2. 5v/3v system figure 9. power supply arrangement
asahi kasei [ak4523] m0021-e-03 1999/12 - 17 - 1. grounding and power supply decoupling the ak4523 requires careful attention to power supply and grounding arrangements. va and vd are usually supplied from analog supply in system. alternatively if va and vd are supplied separately, the power up sequence is not critical. agnd and dgnd of the ak4523 should be connected to analog ground plane. system analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as near to the ak4523 as possible, with the small value ceramic capacitor being the nearest. 2. voltage reference the differential voltage between vrefh and agnd sets the analog input/output range. vrefh pin is normally connected to va with a 0.1f ceramic capacitor. vcom is a signal ground of this chip. an electrolytic capacitor 10f parallel with a 0.1f ceramic capacitor attached to vcom pin eliminates the effects of high frequency noise. no load current may be drawn from vcom pin. all signals, especially clocks, should be kept away from the vrefh and vcom pins in order to avoid unwanted coupling into the ak4523. 3. analog inputs the adc inputs are differential and internally biased to the common voltage (va/2) with 25k w (typ) resistance. figure 7 is a circuit example which analog signal is input by single end. the signal can be input from either positive or negative input and the input signal range scales with the supply voltage and nominally 0.6 x vrefh vpp. in case of single ended input, the distortion around full scale degrades compared with differential input. figure 10 is a circuit example which analog signal is input to both positive and negative input and the input signal range scales with the supply voltage and nominally 0.3 x vrefh vpp. the ak4523 can accept input voltages from agnd to va. the adc output data format is 2s complement. the output code is 7ffffh(@20bit) for input above a positive full scale and 80000h(@20bit) for input below a negative fill scale. the ideal code is 00000h(@20bit) with no input signal. the dc offset is removed by the internal hpf. the ak4523 samples the analog inputs at 64fs. the digital filter rejects noise above the stop band except for multiples of 64fs. a simple rc filter (fc=150khz) may be used to attenuate any noise around 64fs and most audio signals do not have significant energy at 64fs. ak4523 1.5nf 330 + vop=va=5v signal 10k 330 0.1u 22u 4.7k 10k 3.2vpp 1.5vpp 2 3 4 5 ainr+ ainr- ainl- ainl+ 10k vop 4.7k vop 4.7k 10u bias same circuit 1.5vpp njm2100 + + - - figure 10. differential input buffer example
asahi kasei [ak4523] m0021-e-03 1999/12 - 18 - 4. analog outputs the analog outputs are also single-ended and centered around the vcom voltage. the input signal range scales with the supply voltage and nominally 0.58 x vrefh vpp. the dac input data format is 2s complement. the output voltage is a positive full scale for 7ffffh(@20bit) and a negative full scale for 80000h(@20bit). the ideal output is vcom voltage for 00000h(@20bit). the internal switched-capacitor filter and continuous-time filter remove most of the noise generated by the delta-sigma modulator of dac beyond the audio passband. dc offsets on analog outputs are eliminated by ac coupling since dac outputs have dc offsets of a few mv. figure 11 shows the example of external op-amp circuit with 6db gain. the output signal is inverted by using the circuit in this case. aoutl 2.9vpp bias vop vop lch out 5.22vpp 10k 18k 27k 10u 4.7k 4.7k 0.1u 10u + - + 27u + + rch op-amp optional amp with 6db gain vop=12v njm5532 figure 11. external analog circuit example (gain=6db)
asahi kasei [ak4523] m0021-e-03 1999/12 - 19 - package 1.0 0.1 0.1 0-10 detail a seating plane note: dimension "*" does not include mold flash. 0.10 0.15-0.05 0.22 0.1 0.65 *9.8 0.2 1.25 0.2 a 1 14 15 28 28pin vsop ( unit: mm ) *5.6 0.2 7.6 0.2 0.5 0.2 +0.1 0.675 n n n n package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder plate
asahi kasei [ak4523] m0021-e-03 1999/12 - 20 - marking akm ak4523vf xxxbyyyyc xxxbyyyyc: data code identifier xxxb: lot number (x: digit number, b: alpha character) yyyyc: assembly data (y: digit number, c: alpha character) important notice these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: (a) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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